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Service both Internal and External watchdog timers


The two watchdogs act as a check on the microprocessor. If it crashes through a power spike or otherwise, one of the watchdog timers will reset the system and the application software will be re-entered. There is an internal watchdog (default 106ms) and also a counter external to the microprocessor in the TDS9 gate array (426ms). Both are reset by many Forth words and normally you will not notice their action, but will time out and restart the system if something goes wrong.

All looping words like BEGIN UNTIL REPEAT DO LOOP etc. service the timers. In addition some words written in machine code that can take a long time to execute also do it. Among these are FIND FILL CMOVE MS WAIT . Of the three delay words REST WAIT MS only the first does not reset the watchdogs. This is only important if using the TDS2020DV piggyback because without it the maximum delay for REST (53ms) is less than the watchdog timeout (106ms). Correct operation can be checked on TDS2020DV by feeding a large number to REST . The first of these commands will work, but the second will cause the internal watchdog to reset the card, it takes just a bit too long. Try it:


52000 REST 53000 REST


In application programs written in Forth the presence of the watchdogs can normally be completely forgotten. A single loop of 107ms or more would need a watchdog service; in this case include the word WDT in the loop.

The blue reset button, external resets and errors like watchdog timeouts normally give warm restarts into your application program. Even the word COLD is not as cold as possible-it does not corrupt the board clock for example. To get a full cold initialisation, incorporate file #DOGCOLD.TDS. Also use it as a model to vector watchdog, invalid instruction and address faults to your own error handling code.

See flow diagram in STAND-ALONE SYSTEMS, page 232, to understand the default actions of watchdog and other restarts.


The external watchdog timer is independent of the microprocessor. It is a multistage binary divider in the gate array and is fed directly from the E clock. After the divider is reset by a watchdog service a time of 426ms passes. Then the open drain output (similar to open collector) is pulled low for 5s. This resets the card exactly as pulling down the external reset on pin c23 would do, giving your program a warm restart. Installation of file #DOGCOLD.TDS will provide a full cold start as if from power-up.


The internal watchdog is described most fully in Section 13 of the Hardware Manual. On power-up it is already set in operation with an overflow interval of 106.66ms. By changing data in watchdog registers this can be altered to any of 8 values in the range 52s to 106ms.

When the watchdog times out it causes a Non-Masked Interrupt. By default, when an NMI occurs the system examines the watchdog overflow flag. If set, the exception is cleared and a restart is made with the message WATCHDOG put to the serial port. See INTERRUPTS, page 165, for a flow diagram of the NMI action. The internal watchdog is disabled while using an exposed Flash-EEPROM.

PROCESSOR TRAPS, page 147, has an example of redirection to a user-defined word. See ERRORS WHEN MULTITASKING, page 199, for the correct handling in a multitasked system.


When writing assembler programs it is essential to remember the watchdogs. The external watchdog is serviced by writing any data into the memory address area hex 8160 to 816F, the internal watchdog service by writing hex 5A00 to address FFEC. The maximum unserviced intervals and the assembly code are shown below. Generally you would include both once per loop.



B $8160 )) R3 MOVTPE,

( less than every 426ms)


$FFEC )) $5A00 ## MOVIM,

( less than every 106ms)

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